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| SL74LS245 Octal 3-State Noninverting Bus Transceiver These octal bus transceiver are designed for asynchronous twoway communication between data buses. The control function implementation minimized external timing requirements. The device allows data transmission from the A bus to the B bus or from the B bus to the A bus depending upon the logic level at the directional control (DIR) input. The enable input(E) can be used to disable the device so that the buses are effectively isolated. * Bidirectional Bus Transceiver in a High-Density 20-Pin Package * 3-state Outputs Dirve Bus Lines Directly * P-N-P Inputs D-C Loading on Bus Lines * Hysteresis at Bus Inputs Improve Noise Margins * Typical Propagation Delay Times; Port to Port ... 8 ns ORDERING INFORMATION SL74LS245N Plastic SL74LS245D SOIC TA = 0 to 70 C for all packages PIN ASSIGNMENT LOGIC DIAGRAM FUNCTION TABLE Control Inputs Output Enable L PIN 20=VCC PIN 10 = GND Direction L Operation Data Transmitted from Bus B to Bus A Data Transmitted from Bus A to Bus B Buses Isolated (High Impedance State) L H H X X = don't care SLS System Logic Semiconductor SL74LS245 MAXIMUM RATINGS * Symbol VCC VIN VOUT Tstg * Parameter Supply Voltage Input Voltage Output Voltage Storage Temperature Range Value 7.0 7.0 5.5 -65 to +150 Unit V V V C Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. RECOMMENDED OPERATING CONDITIONS Symbol VCC VIH VIL IOH IOL TA Supply Voltage High Level Input Voltage Low Level Input Voltage High Level Output Current Low Level Output Current Ambient Temperature Range 0 Parameter Min 4.75 2.0 0.8 -15 24 +70 Max 5.25 Unit V V V mA mA C DC ELECTRICAL CHARACTERISTICS over full operating conditions Guaranteed Limit Symbol VIK VOH Parameter Input Clamp Voltage High Level Output Voltage Test Conditions VCC = min, IIN = -18 mA VCC = min, IOH = -1.0 mA VCC = min, IOH = -3.0 mA VCC = min, IOH = -15 mA VOL Low Level Output Voltage VCC = min, IOL = 12 mA VCC = min, IOL = 24 mA VT+ - VTIOZH IOZL IIH Hysteresis Output Off Current HIGH Output Off Current LOW High Level Input Current VCC = min VCC = max, VOUT = 2.7 V VCC = max, VOUT = 0.4 V VCC = max, VIN = 2.7 V VCC = max, VIN = 5.5 V (A or B) VCC = max, VIN = 7.0 V for Pin1, Pin 19 IIL IO ICC Low Level Input Current Output Short Circuit Current Supply Current Outputs High Outputs Low All outputs disable VCC = max, VIN = 0.4 V VCC = max, VO =0 V (Note 1) VCC = max Outputs open -40 0.2 20 -0.2 20 0.1 0.1 -0.2 -225 70 90 95 mA mA mA 2.7 2.4 2.0 0.4 0.5 V A mA A mA V Min Max -1.5 Unit V V SLS System Logic Semiconductor SL74LS245 Note 1: Not more thanone output should be shorted at a time, and duration of the short-circuit should not exceed one second. AC ELECTRICAL CHARACTERISTICS (TA = 25C, VCC = 5.0 V, tr = 15 ns,, tf = 6.0 ns) Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ Parameter Propagation Delay Time, Low-to-High Level Output (from A or B to Output) Propagation Delay Time, High-to-Low Level Output (from A or B to Output) Output Enable Time to High Level (from OE to Output) Output Enable Time to Low Level (from OE to Output) Output Disable Time from High Level (from OE to Output) Output Disable Time from Low Level (from OE to Output) CL = 5 pF RL = 667 25 ns CL = 45 pF, RL = 667 Test Condition Min Max 12 12 40 40 25 Unit ns ns ns ns ns tPZL - S1 closed, S2 opened tPZH- S1 opened, S2 closed tPLZ, t PHZ - S1 and S2 closed Figure 1. Switching Waveforms (See Figure 3) Figure 2. Switching Waveforms (See Figure 4) NOTES A. CL includes probe and jig capacitance. B. All diodes are 1N916 or 1N3064. Figure 3. Test Circuit NOTES A. CL includes probe and jig capacitance. B. All diodes are 1N916 or 1N3064. Figure 4. Test Circuit SLS System Logic Semiconductor SL74LS245 EXPANDED LOGIC DIAGRAM SLS System Logic Semiconductor |
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